/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Wes_Regs.h                                                                                *
 *  \brief    This file contains interface header for Wes driver                                        *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2024/12/13     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/
#ifndef WES_REG_H
#define WES_REG_H
/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/

/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/

/********************************************************************************************************
 *                                 Private Macro definition                                             *
 *******************************************************************************************************/

#define WES_FUNC_CTRL_OFF  0x0U

#define BM_WES_FUNC_CTRL_FUNC_CLK_MON_EN  (0x01U << 22U)

#define BM_WES_FUNC_CTRL_FUNC_CLK_EN  (0x01U << 21U)

#define BM_WES_FUNC_CTRL_EXT_CLK_ACTIVE  (0x01U << 20U)

#define BM_WES_FUNC_CTRL_FS_32K_ACTIVE  (0x01U << 19U)

#define BM_WES_FUNC_CTRL_FS_24M_ACTIVE  (0x01U << 18U)

#define FM_WES_FUNC_CTRL_FUNC_CLK_SEL  (0x3U << 16U)
#define FV_WES_FUNC_CTRL_FUNC_CLK_SEL(v) \
  (((v) << 16U) & FM_WES_FUNC_CTRL_FUNC_CLK_SEL)
#define GFV_WES_FUNC_CTRL_FUNC_CLK_SEL(v) \
  (((v) & FM_WES_FUNC_CTRL_FUNC_CLK_SEL) >> 16U)

#define BM_WES_FUNC_CTRL_ANA_WORK_MODE  (0x01U << 14U)

#define BM_WES_FUNC_CTRL_DIG_WORK_MODE  (0x01U << 13U)

#define FM_WES_FUNC_CTRL_SAMP_NUM  (0x3U << 11U)
#define FV_WES_FUNC_CTRL_SAMP_NUM(v) \
  (((v) << 11U) & FM_WES_FUNC_CTRL_SAMP_NUM)
#define GFV_WES_FUNC_CTRL_SAMP_NUM(v) \
  (((v) & FM_WES_FUNC_CTRL_SAMP_NUM) >> 11U)

#define BM_WES_FUNC_CTRL_TRIGGER_SEL  (0x01U << 10U)

#define BM_WES_FUNC_CTRL_WES_WORK_MODE  (0x01U << 9U)

#define FM_WES_FUNC_CTRL_DSEL_NUM  (0x7U << 6U)
#define FV_WES_FUNC_CTRL_DSEL_NUM(v) \
  (((v) << 6U) & FM_WES_FUNC_CTRL_DSEL_NUM)
#define GFV_WES_FUNC_CTRL_DSEL_NUM(v) \
  (((v) & FM_WES_FUNC_CTRL_DSEL_NUM) >> 6U)

#define FM_WES_FUNC_CTRL_ANA_TRG_SEL  (0x3U << 4U)
#define FV_WES_FUNC_CTRL_ANA_TRG_SEL(v) \
  (((v) << 4U) & FM_WES_FUNC_CTRL_ANA_TRG_SEL)
#define GFV_WES_FUNC_CTRL_ANA_TRG_SEL(v) \
  (((v) & FM_WES_FUNC_CTRL_ANA_TRG_SEL) >> 4U)

#define FM_WES_FUNC_CTRL_DIG_TRG_SEL  (0x3U << 2U)
#define FV_WES_FUNC_CTRL_DIG_TRG_SEL(v) \
  (((v) << 2U) & FM_WES_FUNC_CTRL_DIG_TRG_SEL)
#define GFV_WES_FUNC_CTRL_DIG_TRG_SEL(v) \
  (((v) & FM_WES_FUNC_CTRL_DIG_TRG_SEL) >> 2U)

#define BM_WES_FUNC_CTRL_ANA_MODE_EN  (0x01U << 1U)

#define BM_WES_FUNC_CTRL_DIG_MODE_EN  (0x01U << 0U)

#define WES_FUNC_CTRL_1_OFF  0x4U

#define BM_WES_FUNC_CTRL_1_FUNC_CLK_MON_EN  (0x01U << 22U)

#define BM_WES_FUNC_CTRL_1_FUNC_CLK_EN  (0x01U << 21U)

#define BM_WES_FUNC_CTRL_1_EXT_CLK_ACTIVE  (0x01U << 20U)

#define BM_WES_FUNC_CTRL_1_FS_32K_ACTIVE  (0x01U << 19U)

#define BM_WES_FUNC_CTRL_1_FS_24M_ACTIVE  (0x01U << 18U)

#define FM_WES_FUNC_CTRL_1_FUNC_CLK_SEL  (0x3U << 16U)
#define FV_WES_FUNC_CTRL_1_FUNC_CLK_SEL(v) \
  (((v) << 16U) & FM_WES_FUNC_CTRL_1_FUNC_CLK_SEL)
#define GFV_WES_FUNC_CTRL_1_FUNC_CLK_SEL(v) \
  (((v) & FM_WES_FUNC_CTRL_1_FUNC_CLK_SEL) >> 16U)

#define BM_WES_FUNC_CTRL_1_ANA_WORK_MODE  (0x01U << 14U)

#define BM_WES_FUNC_CTRL_1_DIG_WORK_MODE  (0x01U << 13U)

#define FM_WES_FUNC_CTRL_1_SAMP_NUM  (0x3U << 11U)
#define FV_WES_FUNC_CTRL_1_SAMP_NUM(v) \
  (((v) << 11U) & FM_WES_FUNC_CTRL_1_SAMP_NUM)
#define GFV_WES_FUNC_CTRL_1_SAMP_NUM(v) \
  (((v) & FM_WES_FUNC_CTRL_1_SAMP_NUM) >> 11U)

#define BM_WES_FUNC_CTRL_1_TRIGGER_SEL  (0x01U << 10U)

#define BM_WES_FUNC_CTRL_1_WES_WORK_MODE  (0x01U << 9U)

#define FM_WES_FUNC_CTRL_1_DSEL_NUM  (0x7U << 6U)
#define FV_WES_FUNC_CTRL_1_DSEL_NUM(v) \
  (((v) << 6U) & FM_WES_FUNC_CTRL_1_DSEL_NUM)
#define GFV_WES_FUNC_CTRL_1_DSEL_NUM(v) \
  (((v) & FM_WES_FUNC_CTRL_1_DSEL_NUM) >> 6U)

#define FM_WES_FUNC_CTRL_1_ANA_TRG_SEL  (0x3U << 4U)
#define FV_WES_FUNC_CTRL_1_ANA_TRG_SEL(v) \
  (((v) << 4U) & FM_WES_FUNC_CTRL_1_ANA_TRG_SEL)
#define GFV_WES_FUNC_CTRL_1_ANA_TRG_SEL(v) \
  (((v) & FM_WES_FUNC_CTRL_1_ANA_TRG_SEL) >> 4U)

#define FM_WES_FUNC_CTRL_1_DIG_TRG_SEL  (0x3U << 2U)
#define FV_WES_FUNC_CTRL_1_DIG_TRG_SEL(v) \
  (((v) << 2U) & FM_WES_FUNC_CTRL_1_DIG_TRG_SEL)
#define GFV_WES_FUNC_CTRL_1_DIG_TRG_SEL(v) \
  (((v) & FM_WES_FUNC_CTRL_1_DIG_TRG_SEL) >> 2U)

#define BM_WES_FUNC_CTRL_1_ANA_MODE_EN  (0x01U << 1U)

#define BM_WES_FUNC_CTRL_1_DIG_MODE_EN  (0x01U << 0U)

#define WES_SAMP_DATA0_OFF  0x8U

#define FM_WES_SAMP_DATA0_SAMP_DATA0  (0xffffffU << 0U)
#define FV_WES_SAMP_DATA0_SAMP_DATA0(v) \
  (((v) << 0U) & FM_WES_SAMP_DATA0_SAMP_DATA0)
#define GFV_WES_SAMP_DATA0_SAMP_DATA0(v) \
  (((v) & FM_WES_SAMP_DATA0_SAMP_DATA0) >> 0U)

#define WES_SAMP_DATA1_OFF  0xcU

#define FM_WES_SAMP_DATA1_SAMP_DATA4  (0xffU << 24U)
#define FV_WES_SAMP_DATA1_SAMP_DATA4(v) \
  (((v) << 24U) & FM_WES_SAMP_DATA1_SAMP_DATA4)
#define GFV_WES_SAMP_DATA1_SAMP_DATA4(v) \
  (((v) & FM_WES_SAMP_DATA1_SAMP_DATA4) >> 24U)

#define FM_WES_SAMP_DATA1_SAMP_DATA3  (0xffU << 16U)
#define FV_WES_SAMP_DATA1_SAMP_DATA3(v) \
  (((v) << 16U) & FM_WES_SAMP_DATA1_SAMP_DATA3)
#define GFV_WES_SAMP_DATA1_SAMP_DATA3(v) \
  (((v) & FM_WES_SAMP_DATA1_SAMP_DATA3) >> 16U)

#define FM_WES_SAMP_DATA1_SAMP_DATA2  (0xffU << 8U)
#define FV_WES_SAMP_DATA1_SAMP_DATA2(v) \
  (((v) << 8U) & FM_WES_SAMP_DATA1_SAMP_DATA2)
#define GFV_WES_SAMP_DATA1_SAMP_DATA2(v) \
  (((v) & FM_WES_SAMP_DATA1_SAMP_DATA2) >> 8U)

#define FM_WES_SAMP_DATA1_SAMP_DATA1  (0xffU << 0U)
#define FV_WES_SAMP_DATA1_SAMP_DATA1(v) \
  (((v) << 0U) & FM_WES_SAMP_DATA1_SAMP_DATA1)
#define GFV_WES_SAMP_DATA1_SAMP_DATA1(v) \
  (((v) & FM_WES_SAMP_DATA1_SAMP_DATA1) >> 0U)

#define WES_SAMP_DATA2_OFF  0x10U

#define BM_WES_SAMP_DATA2_SAMP_DATA_MODE  (0x01U << 24U)

#define FM_WES_SAMP_DATA2_SAMP_DATA7  (0xffU << 16U)
#define FV_WES_SAMP_DATA2_SAMP_DATA7(v) \
  (((v) << 16U) & FM_WES_SAMP_DATA2_SAMP_DATA7)
#define GFV_WES_SAMP_DATA2_SAMP_DATA7(v) \
  (((v) & FM_WES_SAMP_DATA2_SAMP_DATA7) >> 16U)

#define FM_WES_SAMP_DATA2_SAMP_DATA6  (0xffU << 8U)
#define FV_WES_SAMP_DATA2_SAMP_DATA6(v) \
  (((v) << 8U) & FM_WES_SAMP_DATA2_SAMP_DATA6)
#define GFV_WES_SAMP_DATA2_SAMP_DATA6(v) \
  (((v) & FM_WES_SAMP_DATA2_SAMP_DATA6) >> 8U)

#define FM_WES_SAMP_DATA2_SAMP_DATA5  (0xffU << 0U)
#define FV_WES_SAMP_DATA2_SAMP_DATA5(v) \
  (((v) << 0U) & FM_WES_SAMP_DATA2_SAMP_DATA5)
#define GFV_WES_SAMP_DATA2_SAMP_DATA5(v) \
  (((v) & FM_WES_SAMP_DATA2_SAMP_DATA5) >> 0U)

#define WES_REF_DATA0_OFF  0x14U

#define FM_WES_REF_DATA0_REF_DATA0  (0xffffffU << 0U)
#define FV_WES_REF_DATA0_REF_DATA0(v) \
  (((v) << 0U) & FM_WES_REF_DATA0_REF_DATA0)
#define GFV_WES_REF_DATA0_REF_DATA0(v) \
  (((v) & FM_WES_REF_DATA0_REF_DATA0) >> 0U)

#define WES_REF_DATA1_OFF  0x18U

#define FM_WES_REF_DATA1_REF_DATA4  (0xffU << 24U)
#define FV_WES_REF_DATA1_REF_DATA4(v) \
  (((v) << 24U) & FM_WES_REF_DATA1_REF_DATA4)
#define GFV_WES_REF_DATA1_REF_DATA4(v) \
  (((v) & FM_WES_REF_DATA1_REF_DATA4) >> 24U)

#define FM_WES_REF_DATA1_REF_DATA3  (0xffU << 16U)
#define FV_WES_REF_DATA1_REF_DATA3(v) \
  (((v) << 16U) & FM_WES_REF_DATA1_REF_DATA3)
#define GFV_WES_REF_DATA1_REF_DATA3(v) \
  (((v) & FM_WES_REF_DATA1_REF_DATA3) >> 16U)

#define FM_WES_REF_DATA1_REF_DATA2  (0xffU << 8U)
#define FV_WES_REF_DATA1_REF_DATA2(v) \
  (((v) << 8U) & FM_WES_REF_DATA1_REF_DATA2)
#define GFV_WES_REF_DATA1_REF_DATA2(v) \
  (((v) & FM_WES_REF_DATA1_REF_DATA2) >> 8U)

#define FM_WES_REF_DATA1_REF_DATA1  (0xffU << 0U)
#define FV_WES_REF_DATA1_REF_DATA1(v) \
  (((v) << 0U) & FM_WES_REF_DATA1_REF_DATA1)
#define GFV_WES_REF_DATA1_REF_DATA1(v) \
  (((v) & FM_WES_REF_DATA1_REF_DATA1) >> 0U)

#define WES_REF_DATA2_OFF  0x1cU

#define FM_WES_REF_DATA2_REF_DATA7  (0xffU << 16U)
#define FV_WES_REF_DATA2_REF_DATA7(v) \
  (((v) << 16U) & FM_WES_REF_DATA2_REF_DATA7)
#define GFV_WES_REF_DATA2_REF_DATA7(v) \
  (((v) & FM_WES_REF_DATA2_REF_DATA7) >> 16U)

#define FM_WES_REF_DATA2_REF_DATA6  (0xffU << 8U)
#define FV_WES_REF_DATA2_REF_DATA6(v) \
  (((v) << 8U) & FM_WES_REF_DATA2_REF_DATA6)
#define GFV_WES_REF_DATA2_REF_DATA6(v) \
  (((v) & FM_WES_REF_DATA2_REF_DATA6) >> 8U)

#define FM_WES_REF_DATA2_REF_DATA5  (0xffU << 0U)
#define FV_WES_REF_DATA2_REF_DATA5(v) \
  (((v) << 0U) & FM_WES_REF_DATA2_REF_DATA5)
#define GFV_WES_REF_DATA2_REF_DATA5(v) \
  (((v) & FM_WES_REF_DATA2_REF_DATA5) >> 0U)

#define WES_COMP_DATA0_EN_OFF  0x20U

#define FM_WES_COMP_DATA0_EN_COMP_EN0  (0xffffffU << 0U)
#define FV_WES_COMP_DATA0_EN_COMP_EN0(v) \
  (((v) << 0U) & FM_WES_COMP_DATA0_EN_COMP_EN0)
#define GFV_WES_COMP_DATA0_EN_COMP_EN0(v) \
  (((v) & FM_WES_COMP_DATA0_EN_COMP_EN0) >> 0U)

#define WES_COMP_DATA1_EN_OFF  0x24U

#define FM_WES_COMP_DATA1_EN_COMP_EN4  (0xffU << 24U)
#define FV_WES_COMP_DATA1_EN_COMP_EN4(v) \
  (((v) << 24U) & FM_WES_COMP_DATA1_EN_COMP_EN4)
#define GFV_WES_COMP_DATA1_EN_COMP_EN4(v) \
  (((v) & FM_WES_COMP_DATA1_EN_COMP_EN4) >> 24U)

#define FM_WES_COMP_DATA1_EN_COMP_EN3  (0xffU << 16U)
#define FV_WES_COMP_DATA1_EN_COMP_EN3(v) \
  (((v) << 16U) & FM_WES_COMP_DATA1_EN_COMP_EN3)
#define GFV_WES_COMP_DATA1_EN_COMP_EN3(v) \
  (((v) & FM_WES_COMP_DATA1_EN_COMP_EN3) >> 16U)

#define FM_WES_COMP_DATA1_EN_COMP_EN2  (0xffU << 8U)
#define FV_WES_COMP_DATA1_EN_COMP_EN2(v) \
  (((v) << 8U) & FM_WES_COMP_DATA1_EN_COMP_EN2)
#define GFV_WES_COMP_DATA1_EN_COMP_EN2(v) \
  (((v) & FM_WES_COMP_DATA1_EN_COMP_EN2) >> 8U)

#define FM_WES_COMP_DATA1_EN_COMP_EN1  (0xffU << 0U)
#define FV_WES_COMP_DATA1_EN_COMP_EN1(v) \
  (((v) << 0U) & FM_WES_COMP_DATA1_EN_COMP_EN1)
#define GFV_WES_COMP_DATA1_EN_COMP_EN1(v) \
  (((v) & FM_WES_COMP_DATA1_EN_COMP_EN1) >> 0U)

#define WES_COMP_DATA2_EN_OFF  0x28U

#define FM_WES_COMP_DATA2_EN_COMP_EN7  (0xffU << 16U)
#define FV_WES_COMP_DATA2_EN_COMP_EN7(v) \
  (((v) << 16U) & FM_WES_COMP_DATA2_EN_COMP_EN7)
#define GFV_WES_COMP_DATA2_EN_COMP_EN7(v) \
  (((v) & FM_WES_COMP_DATA2_EN_COMP_EN7) >> 16U)

#define FM_WES_COMP_DATA2_EN_COMP_EN6  (0xffU << 8U)
#define FV_WES_COMP_DATA2_EN_COMP_EN6(v) \
  (((v) << 8U) & FM_WES_COMP_DATA2_EN_COMP_EN6)
#define GFV_WES_COMP_DATA2_EN_COMP_EN6(v) \
  (((v) & FM_WES_COMP_DATA2_EN_COMP_EN6) >> 8U)

#define FM_WES_COMP_DATA2_EN_COMP_EN5  (0xffU << 0U)
#define FV_WES_COMP_DATA2_EN_COMP_EN5(v) \
  (((v) << 0U) & FM_WES_COMP_DATA2_EN_COMP_EN5)
#define GFV_WES_COMP_DATA2_EN_COMP_EN5(v) \
  (((v) & FM_WES_COMP_DATA2_EN_COMP_EN5) >> 0U)

#define WES_STAB_VAL_OFF  0x2cU

#define FM_WES_STAB_VAL_CLK_DIV  (0x7U << 24U)
#define FV_WES_STAB_VAL_CLK_DIV(v) \
  (((v) << 24U) & FM_WES_STAB_VAL_CLK_DIV)
#define GFV_WES_STAB_VAL_CLK_DIV(v) \
  (((v) & FM_WES_STAB_VAL_CLK_DIV) >> 24U)

#define FM_WES_STAB_VAL_SEL_CNT_VAL  (0xffU << 16U)
#define FV_WES_STAB_VAL_SEL_CNT_VAL(v) \
  (((v) << 16U) & FM_WES_STAB_VAL_SEL_CNT_VAL)
#define GFV_WES_STAB_VAL_SEL_CNT_VAL(v) \
  (((v) & FM_WES_STAB_VAL_SEL_CNT_VAL) >> 16U)

#define FM_WES_STAB_VAL_STAB_CNT_VAL  (0xffffU << 0U)
#define FV_WES_STAB_VAL_STAB_CNT_VAL(v) \
  (((v) << 0U) & FM_WES_STAB_VAL_STAB_CNT_VAL)
#define GFV_WES_STAB_VAL_STAB_CNT_VAL(v) \
  (((v) & FM_WES_STAB_VAL_STAB_CNT_VAL) >> 0U)

#define WES_FUNC_SET_DONE_OFF  0x30U

#define BM_WES_FUNC_SET_DONE_SET_DONE_ST  (0x01U << 1U)

#define BM_WES_FUNC_SET_DONE_SET_DONE  (0x01U << 0U)

#define WES_ANA_CTL_OFF  0x40U

#define FM_WES_ANA_CTL_SADC_DATA  (0xffffU << 16U)
#define FV_WES_ANA_CTL_SADC_DATA(v) \
  (((v) << 16U) & FM_WES_ANA_CTL_SADC_DATA)
#define GFV_WES_ANA_CTL_SADC_DATA(v) \
  (((v) & FM_WES_ANA_CTL_SADC_DATA) >> 16U)

#define FM_WES_ANA_CTL_SADC_TID_BW  (0xffU << 8U)
#define FV_WES_ANA_CTL_SADC_TID_BW(v) \
  (((v) << 8U) & FM_WES_ANA_CTL_SADC_TID_BW)
#define GFV_WES_ANA_CTL_SADC_TID_BW(v) \
  (((v) & FM_WES_ANA_CTL_SADC_TID_BW) >> 8U)

#define FM_WES_ANA_CTL_SADC_TID_FW  (0xffU << 0U)
#define FV_WES_ANA_CTL_SADC_TID_FW(v) \
  (((v) << 0U) & FM_WES_ANA_CTL_SADC_TID_FW)
#define GFV_WES_ANA_CTL_SADC_TID_FW(v) \
  (((v) & FM_WES_ANA_CTL_SADC_TID_FW) >> 0U)

#define WES_ANA_TOUT_CTL_OFF  0x44U

#define BM_WES_ANA_TOUT_CTL_WDT_EN  (0x01U << 16U)

#define FM_WES_ANA_TOUT_CTL_TOUT_VAL  (0xffffU << 0U)
#define FV_WES_ANA_TOUT_CTL_TOUT_VAL(v) \
  (((v) << 0U) & FM_WES_ANA_TOUT_CTL_TOUT_VAL)
#define GFV_WES_ANA_TOUT_CTL_TOUT_VAL(v) \
  (((v) & FM_WES_ANA_TOUT_CTL_TOUT_VAL) >> 0U)

#define WES_RSVD_OFF  0x50U

#define FM_WES_RSVD_RES_RES  (0xffffffffU << 0U)
#define FV_WES_RSVD_RES_RES(v) \
  (((v) << 0U) & FM_WES_RSVD_RES_RES)
#define GFV_WES_RSVD_RES_RES(v) \
  (((v) & FM_WES_RSVD_RES_RES) >> 0U)

#define WES_SAMP_DATA0_RED_OFF  0x58U

#define FM_WES_SAMP_DATA0_RED_SAMP_DATA0  (0xffffffU << 0U)
#define FV_WES_SAMP_DATA0_RED_SAMP_DATA0(v) \
  (((v) << 0U) & FM_WES_SAMP_DATA0_RED_SAMP_DATA0)
#define GFV_WES_SAMP_DATA0_RED_SAMP_DATA0(v) \
  (((v) & FM_WES_SAMP_DATA0_RED_SAMP_DATA0) >> 0U)

#define WES_SAMP_DATA1_RED_OFF  0x5cU

#define FM_WES_SAMP_DATA1_RED_SAMP_DATA4  (0xffU << 24U)
#define FV_WES_SAMP_DATA1_RED_SAMP_DATA4(v) \
  (((v) << 24U) & FM_WES_SAMP_DATA1_RED_SAMP_DATA4)
#define GFV_WES_SAMP_DATA1_RED_SAMP_DATA4(v) \
  (((v) & FM_WES_SAMP_DATA1_RED_SAMP_DATA4) >> 24U)

#define FM_WES_SAMP_DATA1_RED_SAMP_DATA3  (0xffU << 16U)
#define FV_WES_SAMP_DATA1_RED_SAMP_DATA3(v) \
  (((v) << 16U) & FM_WES_SAMP_DATA1_RED_SAMP_DATA3)
#define GFV_WES_SAMP_DATA1_RED_SAMP_DATA3(v) \
  (((v) & FM_WES_SAMP_DATA1_RED_SAMP_DATA3) >> 16U)

#define FM_WES_SAMP_DATA1_RED_SAMP_DATA2  (0xffU << 8U)
#define FV_WES_SAMP_DATA1_RED_SAMP_DATA2(v) \
  (((v) << 8U) & FM_WES_SAMP_DATA1_RED_SAMP_DATA2)
#define GFV_WES_SAMP_DATA1_RED_SAMP_DATA2(v) \
  (((v) & FM_WES_SAMP_DATA1_RED_SAMP_DATA2) >> 8U)

#define FM_WES_SAMP_DATA1_RED_SAMP_DATA1  (0xffU << 0U)
#define FV_WES_SAMP_DATA1_RED_SAMP_DATA1(v) \
  (((v) << 0U) & FM_WES_SAMP_DATA1_RED_SAMP_DATA1)
#define GFV_WES_SAMP_DATA1_RED_SAMP_DATA1(v) \
  (((v) & FM_WES_SAMP_DATA1_RED_SAMP_DATA1) >> 0U)

#define WES_SAMP_DATA2_RED_OFF  0x60U

#define BM_WES_SAMP_DATA2_RED_SAMP_DATA_MODE  (0x01U << 24U)

#define FM_WES_SAMP_DATA2_RED_SAMP_DATA7  (0xffU << 16U)
#define FV_WES_SAMP_DATA2_RED_SAMP_DATA7(v) \
  (((v) << 16U) & FM_WES_SAMP_DATA2_RED_SAMP_DATA7)
#define GFV_WES_SAMP_DATA2_RED_SAMP_DATA7(v) \
  (((v) & FM_WES_SAMP_DATA2_RED_SAMP_DATA7) >> 16U)

#define FM_WES_SAMP_DATA2_RED_SAMP_DATA6  (0xffU << 8U)
#define FV_WES_SAMP_DATA2_RED_SAMP_DATA6(v) \
  (((v) << 8U) & FM_WES_SAMP_DATA2_RED_SAMP_DATA6)
#define GFV_WES_SAMP_DATA2_RED_SAMP_DATA6(v) \
  (((v) & FM_WES_SAMP_DATA2_RED_SAMP_DATA6) >> 8U)

#define FM_WES_SAMP_DATA2_RED_SAMP_DATA5  (0xffU << 0U)
#define FV_WES_SAMP_DATA2_RED_SAMP_DATA5(v) \
  (((v) << 0U) & FM_WES_SAMP_DATA2_RED_SAMP_DATA5)
#define GFV_WES_SAMP_DATA2_RED_SAMP_DATA5(v) \
  (((v) & FM_WES_SAMP_DATA2_RED_SAMP_DATA5) >> 0U)

#define WES_REF_DATA0_RED_OFF  0x64U

#define FM_WES_REF_DATA0_RED_REF_DATA0  (0xffffffU << 0U)
#define FV_WES_REF_DATA0_RED_REF_DATA0(v) \
  (((v) << 0U) & FM_WES_REF_DATA0_RED_REF_DATA0)
#define GFV_WES_REF_DATA0_RED_REF_DATA0(v) \
  (((v) & FM_WES_REF_DATA0_RED_REF_DATA0) >> 0U)

#define WES_REF_DATA1_RED_OFF  0x68U

#define FM_WES_REF_DATA1_RED_REF_DATA4  (0xffU << 24U)
#define FV_WES_REF_DATA1_RED_REF_DATA4(v) \
  (((v) << 24U) & FM_WES_REF_DATA1_RED_REF_DATA4)
#define GFV_WES_REF_DATA1_RED_REF_DATA4(v) \
  (((v) & FM_WES_REF_DATA1_RED_REF_DATA4) >> 24U)

#define FM_WES_REF_DATA1_RED_REF_DATA3  (0xffU << 16U)
#define FV_WES_REF_DATA1_RED_REF_DATA3(v) \
  (((v) << 16U) & FM_WES_REF_DATA1_RED_REF_DATA3)
#define GFV_WES_REF_DATA1_RED_REF_DATA3(v) \
  (((v) & FM_WES_REF_DATA1_RED_REF_DATA3) >> 16U)

#define FM_WES_REF_DATA1_RED_REF_DATA2  (0xffU << 8U)
#define FV_WES_REF_DATA1_RED_REF_DATA2(v) \
  (((v) << 8U) & FM_WES_REF_DATA1_RED_REF_DATA2)
#define GFV_WES_REF_DATA1_RED_REF_DATA2(v) \
  (((v) & FM_WES_REF_DATA1_RED_REF_DATA2) >> 8U)

#define FM_WES_REF_DATA1_RED_REF_DATA1  (0xffU << 0U)
#define FV_WES_REF_DATA1_RED_REF_DATA1(v) \
  (((v) << 0U) & FM_WES_REF_DATA1_RED_REF_DATA1)
#define GFV_WES_REF_DATA1_RED_REF_DATA1(v) \
  (((v) & FM_WES_REF_DATA1_RED_REF_DATA1) >> 0U)

#define WES_REF_DATA2_RED_OFF  0x6cU

#define FM_WES_REF_DATA2_RED_REF_DATA7  (0xffU << 16U)
#define FV_WES_REF_DATA2_RED_REF_DATA7(v) \
  (((v) << 16U) & FM_WES_REF_DATA2_RED_REF_DATA7)
#define GFV_WES_REF_DATA2_RED_REF_DATA7(v) \
  (((v) & FM_WES_REF_DATA2_RED_REF_DATA7) >> 16U)

#define FM_WES_REF_DATA2_RED_REF_DATA6  (0xffU << 8U)
#define FV_WES_REF_DATA2_RED_REF_DATA6(v) \
  (((v) << 8U) & FM_WES_REF_DATA2_RED_REF_DATA6)
#define GFV_WES_REF_DATA2_RED_REF_DATA6(v) \
  (((v) & FM_WES_REF_DATA2_RED_REF_DATA6) >> 8U)

#define FM_WES_REF_DATA2_RED_REF_DATA5  (0xffU << 0U)
#define FV_WES_REF_DATA2_RED_REF_DATA5(v) \
  (((v) << 0U) & FM_WES_REF_DATA2_RED_REF_DATA5)
#define GFV_WES_REF_DATA2_RED_REF_DATA5(v) \
  (((v) & FM_WES_REF_DATA2_RED_REF_DATA5) >> 0U)

#define WES_COMP_DATA0_EN_RED_OFF  0x70U

#define FM_WES_COMP_DATA0_EN_RED_COMP_EN0  (0xffffffU << 0U)
#define FV_WES_COMP_DATA0_EN_RED_COMP_EN0(v) \
  (((v) << 0U) & FM_WES_COMP_DATA0_EN_RED_COMP_EN0)
#define GFV_WES_COMP_DATA0_EN_RED_COMP_EN0(v) \
  (((v) & FM_WES_COMP_DATA0_EN_RED_COMP_EN0) >> 0U)

#define WES_COMP_DATA1_EN_RED_OFF  0x74U

#define FM_WES_COMP_DATA1_EN_RED_COMP_EN4  (0xffU << 24U)
#define FV_WES_COMP_DATA1_EN_RED_COMP_EN4(v) \
  (((v) << 24U) & FM_WES_COMP_DATA1_EN_RED_COMP_EN4)
#define GFV_WES_COMP_DATA1_EN_RED_COMP_EN4(v) \
  (((v) & FM_WES_COMP_DATA1_EN_RED_COMP_EN4) >> 24U)

#define FM_WES_COMP_DATA1_EN_RED_COMP_EN3  (0xffU << 16U)
#define FV_WES_COMP_DATA1_EN_RED_COMP_EN3(v) \
  (((v) << 16U) & FM_WES_COMP_DATA1_EN_RED_COMP_EN3)
#define GFV_WES_COMP_DATA1_EN_RED_COMP_EN3(v) \
  (((v) & FM_WES_COMP_DATA1_EN_RED_COMP_EN3) >> 16U)

#define FM_WES_COMP_DATA1_EN_RED_COMP_EN2  (0xffU << 8U)
#define FV_WES_COMP_DATA1_EN_RED_COMP_EN2(v) \
  (((v) << 8U) & FM_WES_COMP_DATA1_EN_RED_COMP_EN2)
#define GFV_WES_COMP_DATA1_EN_RED_COMP_EN2(v) \
  (((v) & FM_WES_COMP_DATA1_EN_RED_COMP_EN2) >> 8U)

#define FM_WES_COMP_DATA1_EN_RED_COMP_EN1  (0xffU << 0U)
#define FV_WES_COMP_DATA1_EN_RED_COMP_EN1(v) \
  (((v) << 0U) & FM_WES_COMP_DATA1_EN_RED_COMP_EN1)
#define GFV_WES_COMP_DATA1_EN_RED_COMP_EN1(v) \
  (((v) & FM_WES_COMP_DATA1_EN_RED_COMP_EN1) >> 0U)

#define WES_COMP_DATA2_EN_RED_OFF  0x78U

#define FM_WES_COMP_DATA2_EN_RED_COMP_EN7  (0xffU << 16U)
#define FV_WES_COMP_DATA2_EN_RED_COMP_EN7(v) \
  (((v) << 16U) & FM_WES_COMP_DATA2_EN_RED_COMP_EN7)
#define GFV_WES_COMP_DATA2_EN_RED_COMP_EN7(v) \
  (((v) & FM_WES_COMP_DATA2_EN_RED_COMP_EN7) >> 16U)

#define FM_WES_COMP_DATA2_EN_RED_COMP_EN6  (0xffU << 8U)
#define FV_WES_COMP_DATA2_EN_RED_COMP_EN6(v) \
  (((v) << 8U) & FM_WES_COMP_DATA2_EN_RED_COMP_EN6)
#define GFV_WES_COMP_DATA2_EN_RED_COMP_EN6(v) \
  (((v) & FM_WES_COMP_DATA2_EN_RED_COMP_EN6) >> 8U)

#define FM_WES_COMP_DATA2_EN_RED_COMP_EN5  (0xffU << 0U)
#define FV_WES_COMP_DATA2_EN_RED_COMP_EN5(v) \
  (((v) << 0U) & FM_WES_COMP_DATA2_EN_RED_COMP_EN5)
#define GFV_WES_COMP_DATA2_EN_RED_COMP_EN5(v) \
  (((v) & FM_WES_COMP_DATA2_EN_RED_COMP_EN5) >> 0U)

#define WES_STAB_VAL_RED_OFF  0x7cU

#define FM_WES_STAB_VAL_RED_CLK_DIV  (0x7U << 24U)
#define FV_WES_STAB_VAL_RED_CLK_DIV(v) \
  (((v) << 24U) & FM_WES_STAB_VAL_RED_CLK_DIV)
#define GFV_WES_STAB_VAL_RED_CLK_DIV(v) \
  (((v) & FM_WES_STAB_VAL_RED_CLK_DIV) >> 24U)

#define FM_WES_STAB_VAL_RED_SEL_CNT_VAL  (0xffU << 16U)
#define FV_WES_STAB_VAL_RED_SEL_CNT_VAL(v) \
  (((v) << 16U) & FM_WES_STAB_VAL_RED_SEL_CNT_VAL)
#define GFV_WES_STAB_VAL_RED_SEL_CNT_VAL(v) \
  (((v) & FM_WES_STAB_VAL_RED_SEL_CNT_VAL) >> 16U)

#define FM_WES_STAB_VAL_RED_STAB_CNT_VAL  (0xffffU << 0U)
#define FV_WES_STAB_VAL_RED_STAB_CNT_VAL(v) \
  (((v) << 0U) & FM_WES_STAB_VAL_RED_STAB_CNT_VAL)
#define GFV_WES_STAB_VAL_RED_STAB_CNT_VAL(v) \
  (((v) & FM_WES_STAB_VAL_RED_STAB_CNT_VAL) >> 0U)

#define WES_ANA_CTL_RED_OFF  0x90U

#define FM_WES_ANA_CTL_RED_SADC_DATA  (0xffffU << 16U)
#define FV_WES_ANA_CTL_RED_SADC_DATA(v) \
  (((v) << 16U) & FM_WES_ANA_CTL_RED_SADC_DATA)
#define GFV_WES_ANA_CTL_RED_SADC_DATA(v) \
  (((v) & FM_WES_ANA_CTL_RED_SADC_DATA) >> 16U)

#define FM_WES_ANA_CTL_RED_SADC_TID_BW  (0xffU << 8U)
#define FV_WES_ANA_CTL_RED_SADC_TID_BW(v) \
  (((v) << 8U) & FM_WES_ANA_CTL_RED_SADC_TID_BW)
#define GFV_WES_ANA_CTL_RED_SADC_TID_BW(v) \
  (((v) & FM_WES_ANA_CTL_RED_SADC_TID_BW) >> 8U)

#define FM_WES_ANA_CTL_RED_SADC_TID_FW  (0xffU << 0U)
#define FV_WES_ANA_CTL_RED_SADC_TID_FW(v) \
  (((v) << 0U) & FM_WES_ANA_CTL_RED_SADC_TID_FW)
#define GFV_WES_ANA_CTL_RED_SADC_TID_FW(v) \
  (((v) & FM_WES_ANA_CTL_RED_SADC_TID_FW) >> 0U)

#define WES_ANA_TOUT_CTL_RED_OFF  0x94U

#define BM_WES_ANA_TOUT_CTL_RED_WDT_EN  (0x01U << 16U)

#define FM_WES_ANA_TOUT_CTL_RED_TOUT_VAL  (0xffffU << 0U)
#define FV_WES_ANA_TOUT_CTL_RED_TOUT_VAL(v) \
  (((v) << 0U) & FM_WES_ANA_TOUT_CTL_RED_TOUT_VAL)
#define GFV_WES_ANA_TOUT_CTL_RED_TOUT_VAL(v) \
  (((v) & FM_WES_ANA_TOUT_CTL_RED_TOUT_VAL) >> 0U)

#define TIMER0_COM_CTRL_OFF  0x100U

#define BM_TIMER0_COM_CTRL_CLK_MON_EN  (0x01U << 29U)

#define BM_TIMER0_COM_CTRL_EXT_CLK_ACTIVE_1  (0x01U << 28U)

#define BM_TIMER0_COM_CTRL_FS_32K_ACTIVE_1  (0x01U << 27U)

#define BM_TIMER0_COM_CTRL_FS_24M_ACTIVE_1  (0x01U << 26U)

#define FM_TIMER0_COM_CTRL_CLK_SEL_1  (0x3U << 24U)
#define FV_TIMER0_COM_CTRL_CLK_SEL_1(v) \
  (((v) << 24U) & FM_TIMER0_COM_CTRL_CLK_SEL_1)
#define GFV_TIMER0_COM_CTRL_CLK_SEL_1(v) \
  (((v) & FM_TIMER0_COM_CTRL_CLK_SEL_1) >> 24U)

#define BM_TIMER0_COM_CTRL_CLK_EN  (0x01U << 21U)

#define BM_TIMER0_COM_CTRL_EXT_CLK_ACTIVE  (0x01U << 20U)

#define BM_TIMER0_COM_CTRL_FS_32K_ACTIVE  (0x01U << 19U)

#define BM_TIMER0_COM_CTRL_FS_24M_ACTIVE  (0x01U << 18U)

#define FM_TIMER0_COM_CTRL_CLK_SEL  (0x3U << 16U)
#define FV_TIMER0_COM_CTRL_CLK_SEL(v) \
  (((v) << 16U) & FM_TIMER0_COM_CTRL_CLK_SEL)
#define GFV_TIMER0_COM_CTRL_CLK_SEL(v) \
  (((v) & FM_TIMER0_COM_CTRL_CLK_SEL) >> 16U)

#define BM_TIMER0_COM_CTRL_WORK_MODE  (0x01U << 8U)

#define FM_TIMER0_COM_CTRL_TIMER_CNT_EN  (0xfU << 4U)
#define FV_TIMER0_COM_CTRL_TIMER_CNT_EN(v) \
  (((v) << 4U) & FM_TIMER0_COM_CTRL_TIMER_CNT_EN)
#define GFV_TIMER0_COM_CTRL_TIMER_CNT_EN(v) \
  (((v) & FM_TIMER0_COM_CTRL_TIMER_CNT_EN) >> 4U)

#define FM_TIMER0_COM_CTRL_CLK_DIV_NUM  (0xfU << 0U)
#define FV_TIMER0_COM_CTRL_CLK_DIV_NUM(v) \
  (((v) << 0U) & FM_TIMER0_COM_CTRL_CLK_DIV_NUM)
#define GFV_TIMER0_COM_CTRL_CLK_DIV_NUM(v) \
  (((v) & FM_TIMER0_COM_CTRL_CLK_DIV_NUM) >> 0U)

#define TIMER0_EVENT0_CTRL0_OFF  0x104U

#define FM_TIMER0_EVENT0_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER0_EVENT0_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER0_EVENT0_CTRL0_COMP_VAL)
#define GFV_TIMER0_EVENT0_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER0_EVENT0_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER0_EVENT0_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER0_EVENT0_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER0_EVENT0_CTRL0_OVF_VAL)
#define GFV_TIMER0_EVENT0_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER0_EVENT0_CTRL0_OVF_VAL) >> 0U)

#define TIMER0_EVENT0_CTRL1_OFF  0x108U

#define BM_TIMER0_EVENT0_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER0_EVENT0_CTRL1_PWM_POLAR  (0x01U << 0U)

#define TIMER0_EVENT1_CTRL0_OFF  0x10cU

#define FM_TIMER0_EVENT1_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER0_EVENT1_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER0_EVENT1_CTRL0_COMP_VAL)
#define GFV_TIMER0_EVENT1_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER0_EVENT1_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER0_EVENT1_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER0_EVENT1_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER0_EVENT1_CTRL0_OVF_VAL)
#define GFV_TIMER0_EVENT1_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER0_EVENT1_CTRL0_OVF_VAL) >> 0U)

#define TIMER0_EVENT1_CTRL1_OFF  0x110U

#define BM_TIMER0_EVENT1_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER0_EVENT1_CTRL1_PWM_POLAR  (0x01U << 0U)

#define TIMER0_EVENT2_CTRL0_OFF  0x114U

#define FM_TIMER0_EVENT2_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER0_EVENT2_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER0_EVENT2_CTRL0_COMP_VAL)
#define GFV_TIMER0_EVENT2_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER0_EVENT2_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER0_EVENT2_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER0_EVENT2_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER0_EVENT2_CTRL0_OVF_VAL)
#define GFV_TIMER0_EVENT2_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER0_EVENT2_CTRL0_OVF_VAL) >> 0U)

#define TIMER0_EVENT2_CTRL1_OFF  0x118U

#define BM_TIMER0_EVENT2_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER0_EVENT2_CTRL1_PWM_POLAR  (0x01U << 0U)

#define TIMER0_EVENT3_CTRL0_OFF  0x11cU

#define FM_TIMER0_EVENT3_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER0_EVENT3_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER0_EVENT3_CTRL0_COMP_VAL)
#define GFV_TIMER0_EVENT3_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER0_EVENT3_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER0_EVENT3_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER0_EVENT3_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER0_EVENT3_CTRL0_OVF_VAL)
#define GFV_TIMER0_EVENT3_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER0_EVENT3_CTRL0_OVF_VAL) >> 0U)

#define TIMER0_EVENT3_CTRL1_OFF  0x120U

#define BM_TIMER0_EVENT3_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER0_EVENT3_CTRL1_PWM_POLAR  (0x01U << 0U)

#define WES_TIMER0_SET_DONE_OFF  0x150U

#define BM_WES_TIMER0_SET_DONE_COM_OVF_UP  (0x01U << 2U)

#define BM_WES_TIMER0_SET_DONE_SET_DONE_ST  (0x01U << 1U)

#define BM_WES_TIMER0_SET_DONE_SET_DONE  (0x01U << 0U)

#define TIMER0_STA_OFF  0x154U

#define BM_TIMER0_STA_OVFW_3_STA  (0x01U << 23U)

#define BM_TIMER0_STA_OVFW_2_STA  (0x01U << 22U)

#define BM_TIMER0_STA_OVFW_1_STA  (0x01U << 21U)

#define BM_TIMER0_STA_OVFW_0_STA  (0x01U << 20U)

#define BM_TIMER0_STA_COMP_3_STA  (0x01U << 19U)

#define BM_TIMER0_STA_COMP_2_STA  (0x01U << 18U)

#define BM_TIMER0_STA_COMP_1_STA  (0x01U << 17U)

#define BM_TIMER0_STA_COMP_0_STA  (0x01U << 16U)

#define BM_TIMER0_STA_OVFW_3_EN  (0x01U << 7U)

#define BM_TIMER0_STA_OVFW_2_EN  (0x01U << 6U)

#define BM_TIMER0_STA_OVFW_1_EN  (0x01U << 5U)

#define BM_TIMER0_STA_OVFW_0_EN  (0x01U << 4U)

#define BM_TIMER0_STA_COMP_3_EN  (0x01U << 3U)

#define BM_TIMER0_STA_COMP_2_EN  (0x01U << 2U)

#define BM_TIMER0_STA_COMP_1_EN  (0x01U << 1U)

#define BM_TIMER0_STA_COMP_0_EN  (0x01U << 0U)

#define TIMER1_COM_CTRL_OFF  0x200U

#define BM_TIMER1_COM_CTRL_CLK_MON_EN  (0x01U << 29U)

#define BM_TIMER1_COM_CTRL_EXT_CLK_ACTIVE_1  (0x01U << 28U)

#define BM_TIMER1_COM_CTRL_FS_32K_ACTIVE_1  (0x01U << 27U)

#define BM_TIMER1_COM_CTRL_FS_24M_ACTIVE_1  (0x01U << 26U)

#define FM_TIMER1_COM_CTRL_CLK_SEL_1  (0x3U << 24U)
#define FV_TIMER1_COM_CTRL_CLK_SEL_1(v) \
  (((v) << 24U) & FM_TIMER1_COM_CTRL_CLK_SEL_1)
#define GFV_TIMER1_COM_CTRL_CLK_SEL_1(v) \
  (((v) & FM_TIMER1_COM_CTRL_CLK_SEL_1) >> 24U)

#define BM_TIMER1_COM_CTRL_CLK_EN  (0x01U << 21U)

#define BM_TIMER1_COM_CTRL_EXT_CLK_ACTIVE  (0x01U << 20U)

#define BM_TIMER1_COM_CTRL_FS_32K_ACTIVE  (0x01U << 19U)

#define BM_TIMER1_COM_CTRL_FS_24M_ACTIVE  (0x01U << 18U)

#define FM_TIMER1_COM_CTRL_CLK_SEL  (0x3U << 16U)
#define FV_TIMER1_COM_CTRL_CLK_SEL(v) \
  (((v) << 16U) & FM_TIMER1_COM_CTRL_CLK_SEL)
#define GFV_TIMER1_COM_CTRL_CLK_SEL(v) \
  (((v) & FM_TIMER1_COM_CTRL_CLK_SEL) >> 16U)

#define BM_TIMER1_COM_CTRL_WORK_MODE  (0x01U << 8U)

#define FM_TIMER1_COM_CTRL_TIMER_CNT_EN  (0xfU << 4U)
#define FV_TIMER1_COM_CTRL_TIMER_CNT_EN(v) \
  (((v) << 4U) & FM_TIMER1_COM_CTRL_TIMER_CNT_EN)
#define GFV_TIMER1_COM_CTRL_TIMER_CNT_EN(v) \
  (((v) & FM_TIMER1_COM_CTRL_TIMER_CNT_EN) >> 4U)

#define FM_TIMER1_COM_CTRL_CLK_DIV_NUM  (0xfU << 0U)
#define FV_TIMER1_COM_CTRL_CLK_DIV_NUM(v) \
  (((v) << 0U) & FM_TIMER1_COM_CTRL_CLK_DIV_NUM)
#define GFV_TIMER1_COM_CTRL_CLK_DIV_NUM(v) \
  (((v) & FM_TIMER1_COM_CTRL_CLK_DIV_NUM) >> 0U)

#define TIMER1_EVENT0_CTRL0_OFF  0x204U

#define FM_TIMER1_EVENT0_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER1_EVENT0_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER1_EVENT0_CTRL0_COMP_VAL)
#define GFV_TIMER1_EVENT0_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER1_EVENT0_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER1_EVENT0_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER1_EVENT0_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER1_EVENT0_CTRL0_OVF_VAL)
#define GFV_TIMER1_EVENT0_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER1_EVENT0_CTRL0_OVF_VAL) >> 0U)

#define TIMER1_EVENT0_CTRL1_OFF  0x208U

#define BM_TIMER1_EVENT0_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER1_EVENT0_CTRL1_PWM_POLAR  (0x01U << 0U)

#define TIMER1_EVENT1_CTRL0_OFF  0x20cU

#define FM_TIMER1_EVENT1_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER1_EVENT1_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER1_EVENT1_CTRL0_COMP_VAL)
#define GFV_TIMER1_EVENT1_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER1_EVENT1_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER1_EVENT1_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER1_EVENT1_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER1_EVENT1_CTRL0_OVF_VAL)
#define GFV_TIMER1_EVENT1_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER1_EVENT1_CTRL0_OVF_VAL) >> 0U)

#define TIMER1_EVENT1_CTRL1_OFF  0x210U

#define BM_TIMER1_EVENT1_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER1_EVENT1_CTRL1_PWM_POLAR  (0x01U << 0U)

#define TIMER1_EVENT2_CTRL0_OFF  0x214U

#define FM_TIMER1_EVENT2_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER1_EVENT2_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER1_EVENT2_CTRL0_COMP_VAL)
#define GFV_TIMER1_EVENT2_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER1_EVENT2_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER1_EVENT2_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER1_EVENT2_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER1_EVENT2_CTRL0_OVF_VAL)
#define GFV_TIMER1_EVENT2_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER1_EVENT2_CTRL0_OVF_VAL) >> 0U)

#define TIMER1_EVENT2_CTRL1_OFF  0x218U

#define BM_TIMER1_EVENT2_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER1_EVENT2_CTRL1_PWM_POLAR  (0x01U << 0U)

#define TIMER1_EVENT3_CTRL0_OFF  0x21cU

#define FM_TIMER1_EVENT3_CTRL0_COMP_VAL  (0xffffU << 16U)
#define FV_TIMER1_EVENT3_CTRL0_COMP_VAL(v) \
  (((v) << 16U) & FM_TIMER1_EVENT3_CTRL0_COMP_VAL)
#define GFV_TIMER1_EVENT3_CTRL0_COMP_VAL(v) \
  (((v) & FM_TIMER1_EVENT3_CTRL0_COMP_VAL) >> 16U)

#define FM_TIMER1_EVENT3_CTRL0_OVF_VAL  (0xffffU << 0U)
#define FV_TIMER1_EVENT3_CTRL0_OVF_VAL(v) \
  (((v) << 0U) & FM_TIMER1_EVENT3_CTRL0_OVF_VAL)
#define GFV_TIMER1_EVENT3_CTRL0_OVF_VAL(v) \
  (((v) & FM_TIMER1_EVENT3_CTRL0_OVF_VAL) >> 0U)

#define TIMER1_EVENT3_CTRL1_OFF  0x220U

#define BM_TIMER1_EVENT3_CTRL1_DEF_VAL  (0x01U << 1U)

#define BM_TIMER1_EVENT3_CTRL1_PWM_POLAR  (0x01U << 0U)

#define WES_TIMER1_SET_DONE_OFF  0x250U

#define BM_WES_TIMER1_SET_DONE_COM_OVF_UP  (0x01U << 2U)

#define BM_WES_TIMER1_SET_DONE_SET_DONE_ST  (0x01U << 1U)

#define BM_WES_TIMER1_SET_DONE_SET_DONE  (0x01U << 0U)

#define TIMER1_STA_OFF  0x254U

#define BM_TIMER1_STA_OVFW_3_STA  (0x01U << 23U)

#define BM_TIMER1_STA_OVFW_2_STA  (0x01U << 22U)

#define BM_TIMER1_STA_OVFW_1_STA  (0x01U << 21U)

#define BM_TIMER1_STA_OVFW_0_STA  (0x01U << 20U)

#define BM_TIMER1_STA_COMP_3_STA  (0x01U << 19U)

#define BM_TIMER1_STA_COMP_2_STA  (0x01U << 18U)

#define BM_TIMER1_STA_COMP_1_STA  (0x01U << 17U)

#define BM_TIMER1_STA_COMP_0_STA  (0x01U << 16U)

#define BM_TIMER1_STA_OVFW_3_EN  (0x01U << 7U)

#define BM_TIMER1_STA_OVFW_2_EN  (0x01U << 6U)

#define BM_TIMER1_STA_OVFW_1_EN  (0x01U << 5U)

#define BM_TIMER1_STA_OVFW_0_EN  (0x01U << 4U)

#define BM_TIMER1_STA_COMP_3_EN  (0x01U << 3U)

#define BM_TIMER1_STA_COMP_2_EN  (0x01U << 2U)

#define BM_TIMER1_STA_COMP_1_EN  (0x01U << 1U)

#define BM_TIMER1_STA_COMP_0_EN  (0x01U << 0U)

#define TEST_MODE_OFF  0x300U

#define FM_TEST_MODE_TEST_MODE  (0x3U << 4U)
#define FV_TEST_MODE_TEST_MODE(v) \
  (((v) << 4U) & FM_TEST_MODE_TEST_MODE)
#define GFV_TEST_MODE_TEST_MODE(v) \
  (((v) & FM_TEST_MODE_TEST_MODE) >> 4U)

#define BM_TEST_MODE_TEST_MODE_EN_PAR  (0x01U << 1U)

#define BM_TEST_MODE_TEST_MODE_EN  (0x01U << 0U)

#define SELFTEST_MODE_OFF  0x304U

#define WES_LKSTEP_INJ_OFF  0x308U

#define BM_WES_LKSTEP_INJ_ERR_INJ_EN  (0x01U << 31U)

#define FM_WES_LKSTEP_INJ_ERR_INJ_BIT  (0xffffU << 0U)
#define FV_WES_LKSTEP_INJ_ERR_INJ_BIT(v) \
  (((v) << 0U) & FM_WES_LKSTEP_INJ_ERR_INJ_BIT)
#define GFV_WES_LKSTEP_INJ_ERR_INJ_BIT(v) \
  (((v) & FM_WES_LKSTEP_INJ_ERR_INJ_BIT) >> 0U)

#define APB_ERR_INT_OFF(n)  (0x310U + 16U*(n))

#define WDAT_ERR_INJ_OFF(n)  (0x314U + 16U*(n))

#define ECC_ERR_INJ_OFF(n)  (0x318U + 16U*(n))

#define FM_ECC_ERR_INJ_ERR_INJ  (0x7fU << 0U)
#define FV_ECC_ERR_INJ_ERR_INJ(v) \
  (((v) << 0U) & FM_ECC_ERR_INJ_ERR_INJ)
#define GFV_ECC_ERR_INJ_ERR_INJ(v) \
  (((v) & FM_ECC_ERR_INJ_ERR_INJ) >> 0U)

#define WES_ERR_INJ_EN_OFF  0x31cU

#define BM_WES_ERR_INJ_EN_CLK_DIV_ERR_INJ_EN  (0x01U << 4U)

#define BM_WES_ERR_INJ_EN_LOOP_ERR_INJ_EN  (0x01U << 3U)

#define BM_WES_ERR_INJ_EN_WAKP_ERR_INJ_EN  (0x01U << 2U)

#define BM_WES_ERR_INJ_EN_IRQ_ERR_INJ_EN  (0x01U << 1U)

#define BM_WES_ERR_INJ_EN_APB_ERR_INJ_EN  (0x01U << 0U)

#define WES_ERR_INJ_BIT_OFF  0x320U

#define FM_WES_ERR_INJ_BIT_TIMER1_DIV_NUM_INJ  (0x3U << 18U)
#define FV_WES_ERR_INJ_BIT_TIMER1_DIV_NUM_INJ(v) \
  (((v) << 18U) & FM_WES_ERR_INJ_BIT_TIMER1_DIV_NUM_INJ)
#define GFV_WES_ERR_INJ_BIT_TIMER1_DIV_NUM_INJ(v) \
  (((v) & FM_WES_ERR_INJ_BIT_TIMER1_DIV_NUM_INJ) >> 18U)

#define FM_WES_ERR_INJ_BIT_TIMER0_DIV_NUM_INJ  (0x3U << 16U)
#define FV_WES_ERR_INJ_BIT_TIMER0_DIV_NUM_INJ(v) \
  (((v) << 16U) & FM_WES_ERR_INJ_BIT_TIMER0_DIV_NUM_INJ)
#define GFV_WES_ERR_INJ_BIT_TIMER0_DIV_NUM_INJ(v) \
  (((v) & FM_WES_ERR_INJ_BIT_TIMER0_DIV_NUM_INJ) >> 16U)

#define FM_WES_ERR_INJ_BIT_FUNC_DIV_NUM_INJ  (0x3U << 14U)
#define FV_WES_ERR_INJ_BIT_FUNC_DIV_NUM_INJ(v) \
  (((v) << 14U) & FM_WES_ERR_INJ_BIT_FUNC_DIV_NUM_INJ)
#define GFV_WES_ERR_INJ_BIT_FUNC_DIV_NUM_INJ(v) \
  (((v) & FM_WES_ERR_INJ_BIT_FUNC_DIV_NUM_INJ) >> 14U)

#define FM_WES_ERR_INJ_BIT_DSEL_INJ  (0xffU << 6U)
#define FV_WES_ERR_INJ_BIT_DSEL_INJ(v) \
  (((v) << 6U) & FM_WES_ERR_INJ_BIT_DSEL_INJ)
#define GFV_WES_ERR_INJ_BIT_DSEL_INJ(v) \
  (((v) & FM_WES_ERR_INJ_BIT_DSEL_INJ) >> 6U)

#define BM_WES_ERR_INJ_BIT_DSE_INJ  (0x01U << 5U)

#define BM_WES_ERR_INJ_BIT_ASE_INJ  (0x01U << 4U)

#define BM_WES_ERR_INJ_BIT_WAKP_INJ  (0x01U << 3U)

#define BM_WES_ERR_INJ_BIT_UNC_IRQ_INJ  (0x01U << 2U)

#define BM_WES_ERR_INJ_BIT_COR_IRQ_INJ  (0x01U << 1U)

#define BM_WES_ERR_INJ_BIT_WES_IRQ_INJ  (0x01U << 0U)

#define WES_FUSA_INT_OFF  0x330U

#define BM_WES_FUSA_INT_LKSTEP_ERR  (0x01U << 31U)

#define BM_WES_FUSA_INT_WDT_TOUT_ERR  (0x01U << 30U)

#define BM_WES_FUSA_INT_SELFTEST_MODE_ERR  (0x01U << 29U)

#define BM_WES_FUSA_INT_WES_TEST_MODE_ERR  (0x01U << 28U)

#define BM_WES_FUSA_INT_TIMER1_CLK_MON_ERR  (0x01U << 27U)

#define BM_WES_FUSA_INT_TIMER0_CLK_MON_ERR  (0x01U << 26U)

#define BM_WES_FUSA_INT_TIMER1_PWM23_CHECK_ERR  (0x01U << 25U)

#define BM_WES_FUSA_INT_TIMER1_PWM01_CHECK_ERR  (0x01U << 24U)

#define BM_WES_FUSA_INT_TIMER0_PWM23_CHECK_ERR  (0x01U << 23U)

#define BM_WES_FUSA_INT_TIMER0_PWM01_CHECK_ERR  (0x01U << 22U)

#define BM_WES_FUSA_INT_FUNC_ASE_CHECK_ERR  (0x01U << 21U)

#define BM_WES_FUSA_INT_FUNC_DSEL_CHECK_ERR  (0x01U << 20U)

#define BM_WES_FUSA_INT_FUNC_DSE_CHECK_ERR  (0x01U << 19U)

#define BM_WES_FUSA_INT_FUNC_COMP_CHECK_ERR  (0x01U << 18U)

#define BM_WES_FUSA_INT_FUNC_CLK_MON_ERR  (0x01U << 17U)

#define BM_WES_FUSA_INT_FUNC_CFG_CHECK_ERR  (0x01U << 16U)

#define BM_WES_FUSA_INT_LKSTEP_INT_EN  (0x01U << 15U)

#define BM_WES_FUSA_INT_WDT_TOUT_INT_EN  (0x01U << 14U)

#define BM_WES_FUSA_INT_SELFTEST_MODE_INT_EN  (0x01U << 13U)

#define BM_WES_FUSA_INT_TEST_MODE_INT_EN  (0x01U << 12U)

#define BM_WES_FUSA_INT_TIMER1_CLK_INT_EN  (0x01U << 11U)

#define BM_WES_FUSA_INT_TIMER0_CLK_INT_EN  (0x01U << 10U)

#define BM_WES_FUSA_INT_TIMER1_PWM23_INT_EN  (0x01U << 9U)

#define BM_WES_FUSA_INT_TIMER1_PWM01_INT_EN  (0x01U << 8U)

#define BM_WES_FUSA_INT_TIMER0_PWM23_INT_EN  (0x01U << 7U)

#define BM_WES_FUSA_INT_TIMER0_PWM01_INT_EN  (0x01U << 6U)

#define BM_WES_FUSA_INT_FUNC_ASE_LP_INT_EN  (0x01U << 5U)

#define BM_WES_FUSA_INT_FUNC_DSEL_LP_INT_EN  (0x01U << 4U)

#define BM_WES_FUSA_INT_FUNC_DSE_LP_INT_EN  (0x01U << 3U)

#define BM_WES_FUSA_INT_FUNC_COMP_INT_EN  (0x01U << 2U)

#define BM_WES_FUSA_INT_FUNC_CLK_INT_EN  (0x01U << 1U)

#define BM_WES_FUSA_INT_FUNC_CFG_INT_EN  (0x01U << 0U)

#define WES_FUSA_INT_1_OFF  0x334U

#define BM_WES_FUSA_INT_1_INTER_TRG_INT_EN  (0x01U << 1U)

#define BM_WES_FUSA_INT_1_EXT_TRG_INT_EN  (0x01U << 0U)

#define LP_CHECK_OFF  0x340U

#define FM_LP_CHECK_TEST_MODE_STA  (0x3U << 30U)
#define FV_LP_CHECK_TEST_MODE_STA(v) \
  (((v) << 30U) & FM_LP_CHECK_TEST_MODE_STA)
#define GFV_LP_CHECK_TEST_MODE_STA(v) \
  (((v) & FM_LP_CHECK_TEST_MODE_STA) >> 30U)

#define FM_LP_CHECK_PWM_ST  (0xffU << 22U)
#define FV_LP_CHECK_PWM_ST(v) \
  (((v) << 22U) & FM_LP_CHECK_PWM_ST)
#define GFV_LP_CHECK_PWM_ST(v) \
  (((v) & FM_LP_CHECK_PWM_ST) >> 22U)

#define FM_LP_CHECK_SELFTEST_ST  (0x3U << 20U)
#define FV_LP_CHECK_SELFTEST_ST(v) \
  (((v) << 20U) & FM_LP_CHECK_SELFTEST_ST)
#define GFV_LP_CHECK_SELFTEST_ST(v) \
  (((v) & FM_LP_CHECK_SELFTEST_ST) >> 20U)

#define FM_LP_CHECK_DSEL_ST  (0xffffU << 4U)
#define FV_LP_CHECK_DSEL_ST(v) \
  (((v) << 4U) & FM_LP_CHECK_DSEL_ST)
#define GFV_LP_CHECK_DSEL_ST(v) \
  (((v) & FM_LP_CHECK_DSEL_ST) >> 4U)

#define FM_LP_CHECK_DSE_ST  (0x3U << 2U)
#define FV_LP_CHECK_DSE_ST(v) \
  (((v) << 2U) & FM_LP_CHECK_DSE_ST)
#define GFV_LP_CHECK_DSE_ST(v) \
  (((v) & FM_LP_CHECK_DSE_ST) >> 2U)

#define FM_LP_CHECK_ASE_ST  (0x3U << 0U)
#define FV_LP_CHECK_ASE_ST(v) \
  (((v) << 0U) & FM_LP_CHECK_ASE_ST)
#define GFV_LP_CHECK_ASE_ST(v) \
  (((v) & FM_LP_CHECK_ASE_ST) >> 0U)

#define REVISION_OFF  0xfff0U

#define IP_CFG_PARA_OFF  0xfff4U

#define FM_IP_CFG_PARA_TIMER1_CH_NUM  (0xffU << 24U)
#define FV_IP_CFG_PARA_TIMER1_CH_NUM(v) \
  (((v) << 24U) & FM_IP_CFG_PARA_TIMER1_CH_NUM)
#define GFV_IP_CFG_PARA_TIMER1_CH_NUM(v) \
  (((v) & FM_IP_CFG_PARA_TIMER1_CH_NUM) >> 24U)

#define FM_IP_CFG_PARA_TIMER0_CH_NUM  (0xffU << 16U)
#define FV_IP_CFG_PARA_TIMER0_CH_NUM(v) \
  (((v) << 16U) & FM_IP_CFG_PARA_TIMER0_CH_NUM)
#define GFV_IP_CFG_PARA_TIMER0_CH_NUM(v) \
  (((v) & FM_IP_CFG_PARA_TIMER0_CH_NUM) >> 16U)

#define FM_IP_CFG_PARA_ADC_INDEX  (0xffU << 8U)
#define FV_IP_CFG_PARA_ADC_INDEX(v) \
  (((v) << 8U) & FM_IP_CFG_PARA_ADC_INDEX)
#define GFV_IP_CFG_PARA_ADC_INDEX(v) \
  (((v) & FM_IP_CFG_PARA_ADC_INDEX) >> 8U)

#define FM_IP_CFG_PARA_DIG_CH_NUM  (0xffU << 0U)
#define FV_IP_CFG_PARA_DIG_CH_NUM(v) \
  (((v) << 0U) & FM_IP_CFG_PARA_DIG_CH_NUM)
#define GFV_IP_CFG_PARA_DIG_CH_NUM(v) \
  (((v) & FM_IP_CFG_PARA_DIG_CH_NUM) >> 0U)

#endif /* WES_REG_H */
/* End of file */
